Reply To: sampling phase auto-sync

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I remember trying to remove DIVBY2 before and not being able to find a phase value that reduced jitter to an acceptable level. I gave it a try again and was able to find a setting that looked good this time. With divide by 1, changing the phase and resetting either the ossc or video source doesn’t have the random phase change problems after a desync.

The red LED is now constantly lit which is probably due to a clock timing problem this change introduces. Unfortunately, I know very little about PLLs and clocking.