Reply To: sampling phase auto-sync

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#10624
redguy_
Participant

I’ve been trying to implement the sample skip method for solving the 180 degree phase shift problem, but am having trouble debugging my changes. What happens is half the time I get a good image and the other half signal is lost when the pll loses lock after changing sampling phase or after reset of the OSSC/video source. Without my changes it would have been 180 degrees out of phase instead of losing signal.

What I changed:
– Added a flag to double sample rate and clear the DIVBY2 bit in the TVP.
– Doubled the input clock frequency on the 3rd PLL and divided all output clocks by 2. I’m only modifying linex3 M2 and M3 right now. Added a 1/2 output clock to simplify the clock alignment calculation.
– Skip advancing line buffer write pointer every other sample. I don’t think I need to do any alignment since it start with either the first or second of the paired samples. It doesn’t matter which one.
– Synchronize sync signals by checking both current and delayed version since input clock is now 2x.

My guess is when the phase change happens I’m not generating output sync properly. I’ve been slowly adding debug information to the LEDs which is a slow process. Both hsync and vsync are still generated when it loses signal. I also have an entry level 2-channel oscilloscope that probably doesn’t have the bandwidth to measure most of the video signals. Although, it might handle sync. I haven’t tried it yet.

Any suggestions for what to look at? Is there a better way to debug this?

EDIT: Looks like it had something to do with how I was stalling the write pointer. It works now, but I’m not quite sure why. It’s not a very satisfying solution.