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(copypasting marqs response to the question about using MicroSD as memory on Shmups)
the ideal solution for getting more memory in use would be locating soft-CPU’s code segment into on-board flash which has more than enough space. However, running code from SPI flash (or micro-SD) without caches (not supported by Nios II/e) would drop CPU performance to somewhere between 1/50th and 1/100th of current architecture which offers single-cycle access to memory. While the CPU is only doing control tasks, such big drop would likely lead to sluggish UI and slower mode detection. The solution would be to get rid of Nios II, and replace it with an open-core such as OpenRISC, LM32 or RISC-V. However, it’s far from a small task as you’d need to integrate the core to the subsystem, implementing any missing/implementation-specific parts (e.g. JTAG, bootrom&loader, linker scripts) and re-design firmware storage/update procedures. There’s a couple projects like Vectorblox ORCA and FuseSoC which could reduce required integration work, though – I should take a closer look when I have more time.