Why didn’t you just revert those 2 commits I mentioned instead of changing more of the code? With the reverts Fmax on pclk_5x is 158 & 161Mhz and now with your updated code Fmax of pclk_5x is only 137 & 150Mhz. So that is quite lower than the needed 161Mhz.
Because I didn’t got the same results as you did? Do you use the same fitter seed as I committed (or in general the same qpf file)? Do you use the latest quarts prime version?
With the latest build and by stuck at your ‘benchmark’ I got F_max 165MHz and 177MHz.
Most timing violations I have seen are in the PP-pipeline – either between two RAMs or between the two concurrent multiplier. However, launch clock is always pclk_indirect and latch clock one of the pclk_act, which makes me wonder. Shouldn’t be that added as false paths?