Reply To: What causes the HPLL2x phase bug?

NewHome Forums OSSC & OSSC Pro OSSC – Discussion and support What causes the HPLL2x phase bug? Reply To: What causes the HPLL2x phase bug?

#39642
marqs
Participant

To me it just looks like a design flaw in TVP7002, i.e. PLL post-divider alignment is random instead of phase select MSB controlling it. ADC block uses the divided clock so no extra samples are taken and thus no averaging is done.