Reply To: OSSC loses sync when receiving 13.75 Khz H Sync

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January 3, 2023 at 7:55 PM #56219
crippo2
Participant

    Thanks for your response
    I can only surmise that the pixel clock rates changes are software driven in order to overcome a hardware limitation (cost/parts availability/design). The change, evened out over time (and possibly using an internal freewheel PLL within the display) might be the creative solution – who knows why, only that it happens and there is no way I can find out why (Commecially confidential etc)
    As to reconstructing the pixel clock, I would take a commercially available 13.5600Mhz clock and divide it down, by 543 to give me a line length of 73.63us, some 60ns short of 73.69us. The Counter would start from 0 with the onset of the VSync pulse and each HSync pulse. The V Sync pulse would give the absolute counter reset once per frame with the H Sync once per line, relying on the accuracy of the count up to keep line sync in phase with the RGB data.
    I will try your suggestion of adsjusting the HSync tolerance – and thanks for it.
    kind regards