Reply To: OSSC and PS2 intermittent black screen

#62089
marqs
Participant

    It seems that the TV is indeed very sensitive to clock stability. I have updated the test firmware so that FPGA low BW option is now also effective on Line2x / passthru. With both BWs set to low, you should get as stable clock as the board can make out of PS2’s sync. Let me know if that helps. If so, please also try ADC BW=high and FPGA BW=low combination which should minimize sampling jitter which still providing relatively stable output clock. Are you btw running PS2 with standard 480i/576i output in Line2x generic 4:3 processing mode?