Reply To: OSSC and PS2 intermittent black screen

#62106
marqs
Participant

    FPGA BW having no effect on result is unexpected. Are you sure the fw was re-flashed correctly (should show 25th Jun on infoscreen and shortly blackout during FPGA PLL BW change)? If so, I can only think one relevant difference compared to v0.90 which could cause the issue. On v0.90 you can disable Allow “TVP HPLL2x” from sampling opt which should then have exact same clocking as v1.xx where the option is always disabled. Let me know if that results to same behaviour as with v1.xx.