Reply To: Krikzz’s RGB Blaster and OSSC Jitter Issue

[marqs]

If you have v1.8 or modified board, you can try latest development fw. Under sync opt, set ADC PLL BW to low or ultra low to trade in clock jitter for higher sampling jitter which might improve display compatibility. If that doesn’t help, you can additionally try setting FPGA PLL BW to low or enable Allow TVP HPLL2x under compatibility opt.