Reply To: Unstable HSync

[marqs]

Sync signal widths are not important, only the interval on leading edges is. If I understood correctly, you have a stable Vsync interval (at 49.99Hz), but your Hsync is generated without using common reference, and thus the last line is always cut short if the first line is triggered at Vsync trailing edge. This can easily cause the H-PLL to lose lock if the last line is even a few % shorter than previous lines. Even if the PLL is able to maintain lock, the clock jitter propagates to HDMI output and many displays do not tolerate much jitter.

With a suitably selected period, you might be able to minimize the difference in line interval to small enough value. You can additionally tune H-PLL and FPGA PLL bandwidth to a lower value under Sync. Opt which may help to distribute the clock variation to longer time period if they still can maintain lock.