Reply To: Unstable HSync
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Perhaps you could draw a diagram of the pulses to illustrate sync relationships. It’d be indeed better to start vsync pulse aligned to start of hsync, otherwise the signal might get decoded as interlace.
The green LED goes off (equals red LED being lit on native v1.8 board) when either of the following things happen (in addition to detecting IR code):
* PLL inside FPGA loses lock due to sudden change in sampling clock. Note that the PLL is bypassed in passthru and some 2x modes.
* Input vsync leading edge occurs too far from the expected position. This occurs during a mode change or if there is large variation in vsync interval.
Note that the signal goes thru downstream PLLs during (de-)serialization so even if ADC and FPGA PLL are able to maintain lock, something later may not if the clock signal is not clean. With the listed PLL BW settings you might be able to spread out disturbances in time domain, but having a periodic hsync (leading edge) has much bigger impact.
