Reply To: OSSC v1.xx series beta firmware

[marqs]

marqs, I’ve been wondering about this for a while now: would it be possible to take a regular OSSC 1.8, desolder the RAM, add a similar RAM module but with higher capacity and rework the firmware to accept features such as motion adaptive deinterlacing? even if only at say, 2x

OSSC doesn’t have any RAM chip to begin with, it only uses the limited block RAM available on FPGA. The only larger pin compatible FPGA would be EP4CE22 that has 10 additional 1kB RAM blocks, enabling only 2 extra line buffers (of 2048 pixels each). A larger quality of life improvement would be adding a clock generator on board to enable (ideally with above FPGA upgrade) A-LM functionality of Pro, even though it’d have some limitations. That would require PCB update in addition to FW fork which at this point of lifespan has high barrier.