Reply To: SNES De-blur

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January 31, 2017 at 12:41 AM #11032
paulb_nl
Participant

    I am new to Verilog/FPGA so my knowledge is very limited. I have no idea how to change it to a pipelined version. Would it still work in linedouble mode then?

    For the alternative, do you mean something like this? Compare R_act to R_prev and when it has changed increase a register every cycle then if register is 2 do R_pp1 <= apply_reverse_lpf. I guess that wouldnt work with linedouble/generic linetriple.

    Are you willing to make the pipelined version? With your knowledge it will probably take you a few minutes 🙂