Reply To: PLL, what is it?

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February 15, 2018 at 11:41 AM #19306
James-F
Participant

    Thank you.
    So the OSSC is an FPGA controlled TVP7002 which is a brilliant idea. 🙂

    If I understand correctly PLL stabilizes the HSync because HSync is somehow unstable or distorted when VSync is active?;
    and H-PLL pre/post coast are the region in time where the PLL locks/unlocks a more stable HSync signal while the VSync does its job and replaces the unstable HSync with the fixed-HSync while it’s active.
    Please confirm…

    Now that raises few question;
    Why the analog HSync during Vsync so distorted that it requires fixing before digitization?
    Why some consoles require more than other?
    How a CRT handles it?