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#19879
marqs
Participant

Meeting timing requirements is likely to get harder as the design progressively grows, thus leaving less resources for routing. With couple last official firmwares I’ve had to run around 20 iterations with different initial placement seeds to minimize violations. Another challenge is muxing of various clock sources (PLL outputs etc.) which potentially increases skew. Ideally only a single PLL output would be routed to logic and PLL settings could be changed dynamically, but changing PLL configuration (via ALTPLL_RECONFIG) is not very straightforward with Cyclone IV and would likely consume at least 1 M9K. Timing constraints have also been quite a mess with all inter-clock relationships, but I’ve now made a rewrite of those using additional generated_clocks which simplifies SDC and hopefully improves robustness.