Reply To: Low Pass Filter Problem – Amstrad CPC 464

NewHome Forums OSSC & OSSC Pro OSSC – Discussion and support Low Pass Filter Problem – Amstrad CPC 464 Reply To: Low Pass Filter Problem – Amstrad CPC 464

#24919
jesus delmas
Participant

It uses Vsync. Here is the complete.information

The display is controlled by the CRTC and the Gate Array.
The CRTC generates horizontal and vertical sync signals, and can be used to generate a variety of screen displays.
The Gate-Array converts bytes into pixels using the current screen-mode and palette settings.
Therefore we can synchronise with the CRTC, to an exact point where the internal counters are exactly what we want, or to a exact position on the display.
By synchronising to the display cycle any effect using the CRTC and Gate-Array is possible:rasters (Gate-Array)
split-rasters (Gate-Array)
diagonal-rasters (Gate-Array)
vertical rupture/splitting (CRTC)
horizontal rupture/splitting (CRTC)
multiple modes (Gate-Array)
Synchronising using the VSYNC
The VSYNC signal of the CRTC is connected directly to PPI port B, therefore it is possible to test the state of the VSYNC.
It is possible to synchronise to the start of the VSYNC using the following code: e.g.
[size=inherit]ld b,&f5 ;; PPI port B input .wait_vsync in a,(c) ;; [4] read PPI port B input ;; (bit 0 = “1” if vsync is active, ;; or bit 0 = “0” if vsync is in-active) rra ;; [1] put bit 0 into carry flag jp nc,wait_vsync ;; [3] if carry not set, loop, otherwise continue .continue [/size][size=inherit]Note[/size] This code assumes that the VSYNC is not already active before the code is executed.
However, this will not be accurate enough:
At the best, VSYNC will become active exactly when PPI port B is read (on the final execution cycle of the “in a,(c)” instruction), and at the program-counter defined by the “continue” label, we will then be synchronised to 4 cycles (the time for “rra” and “jp” instructions) from the start of the VSYNC signal.
At the worst, we will just miss seeing the VSYNC become active the first time PPI port B is read (since it would become active just after “in a,(c)” has executed), and then it will be another 7 cycles (time for “rra”, “jp nc” and all but the last execution cycle of “in a,(c)”), before the VSYNC is detected. Then when we get to the program-counter defined by “continue” label, we will then be synchronised to 11 cycles from the start of the VSYNC signal. Therefore the timing can differ.
In reality the timing can vary each frame, and depends on the program code following the synchronisation code.
Therefore, if we relied on VSYNC alone our effect would not be stable. For rasters this would mean they would “shake” which is useless for for split rasters