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These issues are likely to be caused by timing violations (rather than code changes) inside FPGA or on its boundary. The tools reported no violations with the initially released image so I have to re-check constraints, but in general it has got progressively harder to make a clean compilation run as more FPGA logic has been allocated for new features which leaves less liberty in placement & routing.
If the alternative build fixes the issues, I’ll replace the original ones with it.
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