Reply To: DExx-vd_isl – horizontal jitter in scaling mode

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October 17, 2022 at 5:57 PM #55380
marqs
Participant

    We have been looking into the issue which seems to manifest in some setups and is related to (external) clock generation and noise caused by it. If you are capable of soldering, there is at least one hack you can try which should significantly improve signal integrity. That involves connecting GPIO pin 2 to GND on DExx board as shown below:

    Scratching some solder mask off the GND plane
    Scratching some solder mask off the GND plane

    Solder blob added between the pin and exposed GND plane
    Solder blob added between the pin and exposed GND plane

    If you perform the hack, please remove DExx from DE10-Nano when not using the DExx firmware/SD card to avoid the situation where any other firmware would drive 1 into that pin while it is connected to GND.

    For those who are unable to solder, I’ve been thinking about a backup solution which would generate clock internally on FPGA. Unfortunately that could be only applied to non-framelock mode and limited number of fixed output modes (e.g. 1080p@60).