Reply To: OSSC loses sync when receiving 13.75 Khz H Sync
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An update from the earlier post.
If appears that the display is responsive to an LVDS pixel clock signal rathar than the H & V Sync signals also sent to it. The 6.678Mhz pixel clock counts cycles and synchronises the H & V Sync signals to them rather than just relying on the pulses created by the Sync generator. this magic hsappens in ICs for which I can find no datasheet, so remedies using similar technology are difficult, requiring an alternative approach
I wonder if a guru might please confirm that the OSSC inputs (and if only some, which ones) will accept and process the 13.75khz HSync rate and a frame rate of 50Hz.
thanks and regards
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This reply was modified 2 years, 11 months ago by
crippo2.
