Reply To: OSSC v1.xx series beta firmware

#56690
marqs
Participant

    The Y channel at the end of cable is probably easiest as I don’t see native component output on the schematic linked. Alternatively I could share sof/stp files which would allow using built-in logic analyzer of Quartus if you are interested trying it out.

    Before going there, try still the latest image and also reducing ‘Vsync threshold’ from sync menu. This new image has the deinterlace issue fixed as well.