Reply To: OSSC dancing pixels Line 5x mode

[marqs]

Due to TX pixel repetition 6x has lower pixel clock between FPGA and transmitter but higher clock on transmitter output than 5x. That indicates a potential timing bottleneck on FPGA (perhaps bad unit?) instead of the transmitter, but it’s certainly more expensive to acquire and swap. You can replace the transmitter but don’t hold up too high hopes on it solving the issue.