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FPGA pins 126 and 127 are used as configuration bits which are read at power-up. Both are connected to GND on official v1.6 HW.
Pin 126: 0= v1.7 or earlier HW . 1= v1.8 HW. Selects the pin where FPGA receives raw separated HSYNC from video ADC.
Pin 127: 0=HDMI model. 1=DVI model. Sets default TX mode
The standard method for the mod leaves these FPGA pins untouched and just runs the single wire as described in opening post. Only downside is that red LED does no more function when done this way.
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