Reply To: OSSC and PS2 intermittent black screen

[marqs]

I made 2 additional test versions which are linked and described below:

T1: This has TVP HPLL2x option restored (has to be enabled under compatibiliy opt). When used together with ADC PLL BW = low, the result should be identical to v0.90
T2: Instead of using HPLL2x with its side effects, this version has expanded range of ADC PLL BW. The new “Low” setting is lower than above and should result to more stable clock at the price of increased jitter