Reply To: OSSC v1.xx series beta firmware

[marqs]

@MiCv2 According to this thread there is basically 2 potential problems. First one is the sync level as I suspected so you should check the following:
* GD revision
* Type of MD2 cable (is sync from composite video pin 4 or csync pin 5)
* Any components (resistors / capacitors) on the sync wire of the cable
When sync level issue is resolved, you should see stable reading on OSSC character display (last vertical Hz digit may still fluctuate due to issue described below).

The second issue is sync jitter inherent to 2600/7800 and the way it’s handled by the sync generator logic on the cart. The jitter couples into output clock and can cause video and/or audio compatibility issues with many displays/AVRs. There is not much OSSC can do about that due to tight line-locking behaviour, but latest development firmware has ADC PLL BW option under sync opt. By setting its value to Low or Ultra Low, you might be able to make output clock more stable at the price of increased sampling jitter, especially at top portion of the screen. You can additionally try enabling “Allow TVP HPLL2x” under compatibility opt.