Reply To: OSSC v1.xx series beta firmware

#63422
marqs
Participant

    @akvankka: some boards seem to have timing issues with high-frequency clock on certain firmware versions that gets reported every now and then. According to the FPGA design tool IO timing should be fully clean, though. Any trivial RTL modification also completely changes timing so it’s hard to debug. I can check if any of my boards have this issue with 1080p/1440p output.