400p mode for retro PC

[marqs]

Maybe we can push 2000 even if it is beyond recommended specs?

Seems like you might be in luck since that surprisingly works on my test unit. No guarantee it will work perfectly on every OSSC, though.

[James-F]

HDMI 1.3 mandates single-link bandwidth of 340 MHz, and according to IT6613 spec sheet:
“The IT6613 is a high-performance HDMI transmitter, fully compatible with HDMI 1.3”
Actually, it’s not a surprise that the IT6613 can do much more than 165Mhz since this value is part of the old “standard” and not actual measured value by the manufacturer.
The quality of the HDMI cable is more important at this point if the IT6613 can push 190MHz.

[marqs]

I doubt HDMI 1.3/1.4 spec actually requires all transmitters to able to meet the maximum 340MHz rate. Even if that was the case, the FPGA logic becomes another bottleneck above ~170MHz (although that can be worked around with pixel repetition if 0.5x samplerate is used).

[James-F]

Thank you very much marqs, can’t wait to test this.

What do you mean “pixel repetition if 0.5x samplerate is used”?
I assume nothing currently using above 170MHz except the 449p Line3x mode, does that need any FPGA Logic?
By FPGA Logic do you mean scanlines and other post processing?
Isn’t halving the samplerate for processing negates the whole purpose of Line3x in 449p?
Sorry for all the questions, I am intrigued and like to learn about the OSSC as much as possible.

Another question:
In 720×400 I have 900 H.samplerate, in Line2x mode and with Upsample2x effectively sampling 1800 times, but with Upsample2x disabled it samples exactly 900 times and doubles that using math, if I’m not mistaken…
Does that mean in Line3x, Upsample2x will be sampling 4000 times or will it be disabled for Line3x? I assume the latter.

[marqs]

The comment about pixel repetition was general, not just for this case. So if IT6613 somehow was able process and output 340MHz pixel clock while FPGA logic pipeline (incl. line buffers) is limited to around 170MHz, one would still able to utilize higher resolution output by duplicating pixel clock (horizontal number of pixels) by enabling pixel repetition on IT6613. That naturally means every other pixel is duplicate, but it could still help with setting correct aspect ratios on higher resolutions. The default presets except the new 1600×400 result into pixel clock below 170MHz.

“Upsample2x” and “Allow TVP HPLL2x” options control how sampling is done internally, and they are applicable only to certain modes. The former never samples higher than what output total is, so it’s not enabled for 1600×400 or similar presets which already have high samplerate to match line3x or higher vertical multiplication. Upsample2x is mainly meant for presets like 480p or 640×400 which are used in line2x in addition to passthru. It just enables user select how horizontal 2x multiplication is done – either 2x sampling on TVP7002 or pixel repetition on IT6613 (which is more straightforward than adding extra 2x multiplication on FPGA).

Allow TVP HPLL2x option on the other hand sets TVP7002 sample at 2x rate internally, but its output is divided by 2 so the timing seen by FPGA is identical regardless of the option. The reason for using this option is that TVP7002 is not very good at low sampling clocks (increased jitter), so the option is enabled for low-res presets which don’t have high samplerate (e.g. basic 240p preset). The downside of the option is that phase is not consistent with it (random 180deg shift) due to bad implementation in TVP7002, so it’s disabled for all optimal modes.

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