Krikzz’s RGB Blaster and OSSC Jitter Issue

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  • #62371
    andychristian
    Participant

      Hey folks,

      I’m using the RGB Blaster from Krikzz on my unmodified AV Famicom and outputting via my OSSC.

      I’m getting the common OSSC “jitter effect” that would normally be fixed by installing the De-Jitter board on top of a NES RGB install. However, seeing as I’m using the RGB Blaster instead of NES RGB, I’m unsure what my options would be.

      Any ideas? (other than using a different scaler)

      Thanks in advance.

      #62392
      marqs
      Participant

        If you have v1.8 or modified board, you can try latest development fw. Under sync opt, set ADC PLL BW to low or ultra low to trade in clock jitter for higher sampling jitter which might improve display compatibility. If that doesn’t help, you can additionally try setting FPGA PLL BW to low or enable Allow TVP HPLL2x under compatibility opt.

        #62396
        andychristian
        Participant

          Thanks marqs, will give that a shot 🙂

          #62445
          andychristian
          Participant

            Hey @marqs, so at the weekend I managed to succuessfully mod my 1.6 board and installed the latest dev FW. While adjusting the ADC PLL and FPGA PLL settings did make my picture more stable (and allowed me to enable 240 optimised mode – something I couldnt do before), I still have shimmering/jitter at the top of the screen (tested on all line x modes, plus a few tvs/monitors).

            Is this just something I will need to accept will happen when using the RGB Blaster with the original OSSC? I’m guessing this wouldn’t be an issue if I upgraded to the OSSC Pro?

            #62472
            marqs
            Participant

              Which combination of the setting you ended using? Unfortunately lower ADC PLL BW makes NES sync jitter more visible which is the tradeoff to get better compatibility. With Pro HW there are more ways to solve the issue without having to sacrifice picture quality.

              #62489
              andychristian
              Participant

                I’m using ADC PLL BW set to Medium (setting to High gives me a blank screen) Also have FPGA PLL BW set to Low (again, High gives me a blank screen). The screen jitter at the top definely is a lot less noticeable than when using previous FW versions. Also, setting the Video In Video LFP to Off reduces the jitter even more without affecting the rest of the image.

                The above is when outputting to a VGA CRT monitor via a DAC (an HP 7540 to be precise) I also get the jitter when using my HDMI TV, however it is more forgiving and allows the ADC and FPGA settings to both be set to high. Also, if I want to hide it, I can do so by setting the output to 5x which crops off the top of the image anyways (adding a vertical mask of 2 on top of that is enough to completly hide the jitter)

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