SNSP-CPU-02 SNES + SuperCIC + RGB Bypass — CSYNC and installation advice

[Jamie Shaw]

Looking for some advice pre-purchase on Borti’s RGB bypass to be installed into a PAL SNSP-CPU-02 SNES, alongside an existing install of Borti’s SuperCIC AIO mod.

Firstly, there seems to be conflicting instructions between VGP and the GitHub repo on how to install in this revision of SNES.  The former seems to remove the caps to the AV out pins, severing the connection, where as the GitHub repo removes transistors whilst replacing resistors at the same time (this isn’t mentioned on VGP).  Not sure what the difference between the two is for, but any help there would be appreciated.  It does seem that those original instructions were for an earlier revision of the board (circa 2016) so may no longer be required, and just lifting the RGB & CSYNC caps is enough?

Secondly, the AIO board already features a buffered CSYNC output, but not sure if this can be passed into the bypass board on the “CS” pad.  If it can, does the buffered CSYNC jumper (J3) need to be open or closed?

For reference, I’ve already gone ahead and physically cut the trace from pin 3 to C46, which is where the buffered CSYNC out from the AIO board is currently soldered to.

Again, any help would be appreciated if any one has a similar install and advice to offer.

• This topic was modified 12 months ago by Jamie Shaw.

[Morpheus_79]

Maybe you can ask ‘borti’ himself:

https://circuit-board.de/forum/index.php/Thread/20199-SNES-RGB-Bypass-f%C3%BCr-PAL-3-Chip-SNES-SNSP-CPU-01-02/

Even though it’s a German forum, they don’t mind if you ask in English.

[Jamie Shaw]

Thanks, I’ll do just that.  Just ended up posting here as VGP sells a version of the board, and was looking for some pre-purchase advice 😅

[Jamie Shaw]

Going through a bit of a roundabout here… 😅

Having posted on the circuit-board.de thread, I was redirected to contact Matt from VGP directly, and in turn, kindly forwarded back to the community here for some further insight.

I might’ve not been clear in my original post, but the Bypass board that I have purchased is the VGP 4.1b board, hence why I am posting here. But due to the differences between it and Borti’s original design, I have some questions about changing it to be suitable with Borti’s AIO SuperCIC / Dejitter board.

Looking into this further, it seems that he does provide instructions on how to connect the AIO board to the bypass board for PAL 1-CHIP models and a couple of modifications required on the bypass board, but unfortunately due to the VGP model being a derived design of Borti’s, I’m unsure what, if any resistors are required to support the CSYNC coming from the AIO board.

For the most part, it seems that the first two resistors connected to the CSYNC input on the bypass board are replaced to better suit the voltage coming out of the AIO board, as well as selection of TTL or 75Ω CSYNC provided to AV Pin 3 — these are R41 and R42 on Borti’s design.  I’m not sure how this translates to the VGP version, if at all, I understand if it’s not a 1:1 derivative.

Borti’s GitHub defines the output of the “raw” CSYNC pad on the AIO board as follows, but I’m not electrical engineering minded enough to decipher which changes are required.

/CS.o raw: (output (2x)) Raw output of the CPLD, which has 3.3V high and 0V low level. Connect it to the video encode, which is pin 8 of the S-ENC or pin 7 of the S-RGB (both chips allows 2.0V for input high, so 3.3V high is sufficient.)

For reference, I have a RetroGamingCable’s 470Ω CSYNC RGB SCART so will be using TTL CSYNC — I’ve already soldered J2 on the board to accomplish this. How this factors into the resistors replacements, again, I’m unsure. It may be that the equivalent of R41 only needs replacing in this regard.

If all else fails, I’ll just leave the CS pad empty and find an alternate-sync SCART.

[TheCorfiot]

Yes it can be a bit of a nightmare…

My advice is use the buffered sync from the scic board

Cut the tracks for RGB at the video out port then stick the rgb board in place.

Run the RGB signals from the mainboard as identified in the docs but use the scic out for csync

[Max]

Hi!

I have a similar console with a SNSP-CPU-02 board. Was it possible to modify it and, if so, what solutions were used for this?

[Jamie Shaw]

I ended up picking up a 1CHIP board and using the RGB Bypass on that one.

I just couldn’t deal with the smearing from the 2 PPUs on the original board 😅

[Author]

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