Troubleshooting FPGA after build.

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  • August 14, 2024 at 6:29 PM #62851
    adami
    Participant

      Hi,

      I’ve build for myself OSSC ver 1.8. I’ve used this firmware image for programming:

      http://www.infocult.com/m/ossc/fw/v1-series/ossc_1.11-aud.jic

      Programming and verification finished successfully, but there no activity from FPGA chip: RESET_N signal stays low and no activity on the I2C bus.

      I’ve verified all the power rails – voltages are correct and stable, CLK signal is 27MHz 3V peak to peak. Programming and verification using USB blaster finishes with success.I’ve even downloaded image back from device after power off/on cycle and it matches original with exception of a couple of bytes at the very end of the image so expect this is some metadata specific to flashing process. Is there anything else I can check to verify what is the source of the problem? Or do I need to go in-depth and start learning how to do FPGA debugging? Any suggestions on how to solve this problem will be much appreciated.

       

      August 19, 2024 at 3:20 PM #62916
      adami
      Participant

        I got this to work, and maybe it will be useful for someone. If all the clk and power signals are fine and it is possible to flash image using JTAG connector but FPGA show no signs of activity then check if R18 (CONF_DONE) is properly connected. In my case that was the source of the problem, once I’ve fixed it OSSC started to work.

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