240p / 288p at double frequency

[smorsked]

Hi, i have a sugestion of improoved 240p/288p for vga crt:s:

Is it possible to display 240p/288p at double frequency with a firmware update? (320×240 120hz and pal equivalent)

When displaying 240p line doubled to 480p with inserted scanlines the image looses some brightness natuarlly(sence half teh screen is blackened). Will it be possible to output 240p at 120hz instead of 240p 60hz?(and pal equivalent). Im asking because when using a vga pc crt most monitors dosnt suport 15khz, only 31khz and above. 240p at 120hz looks amazing and can be displayed on pretty much any a vga pc crt , it would be an amazing improvment in a firmware update if possible.

This feature will be usefull mostly for people wusing vga crt:s in their setups. i doubt this strange signal will be accepted by most other monitors. It will make VGA crt:s comparable to PVM:s and BVM:s if it works though.

my setup is a dell p992

Thanks in advance

Smorsked

[marqs]

Any framerate conversion requires a framebuffer, and OSSC only has memory for a couple line buffers.

[smorsked]

Ah ok. Thank you. Is there perhaps plans for a future board revision with that sort of framebuffer in the future?

[BuckoA51]

That would really be a whole new device, rather than a revision to the OSSC.

[paulb_nl]

Define whole new device. An OSSC revision with a FPGA with more pins for a RAM chip and flexible PLL chip should do it.

[BuckoA51]

A framebuffer based device would be quite different from the current OSSC and have different design considerations for best results, plus lots of new software of course. It’s way more than just slapping a frame buffer on the current OSSC.

[paulb_nl]

Of course the hardest part would be programming the firmware and it would most likely need a separate firmware because of the different FPGA but the framebuffer would be an optional feature. It would not replace the zero lag processing of the current hardware.

With the extra RAM and PLL you can also optionally normalize the output with around 1 to 2ms delay. You don’t need to use a full framebuffer for that.

So with that said I fail to see how it would be quite different. What kind of different design considerations do you have in mind?

[marqs]

Framebuffer and dedicated PLL would not need to replace any existing functionality, but with larger FPGA requirement (basically a BGA which would also require way more advanced PCB) it’d be tempting to select a high-performance model that could not just handle the extra memory but also do more advanced processing, drive 4K etc. Changes like that would put the device in its own league not just in terms of possible features but also unavoidably in cost and complexity (less DIY-friendly). With that in mind, it’d make more sense to implement it as a separate/successor device rather than a new OSSC revision.

[paulb_nl]

Its unfortunate that a larger FPGA is only available in BGA. However, OSSC 2.0 4K confirmed 😀

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