Hello, I’m an aspiring electrical engineer with a lot of questions so please forgive my ignorance.
My question is regarding the OSSC’s chosen FPGA altera chip. What were the primary factors that influenced the selection of this chip? What does the amount of logic elements or logic blocks contribute to running this device. Also does the number of I/O’s matter for this firmware? What were the primary factors that are necessary to run the OSSC firmware. Is there a better reference somewhere online that I’m missing?
I’m curious if anyone has found potential alternative FPGA’s to use, or could suggest for running modified versions of the OSSC software.