The Sega Saturn and the dreaded PLL chip

[SeleDreams]

I’m following since it’s pretty interesting

[walter.comunello]

alright, news. Good news so far.

I’ve built both versions and programmed the 937 one. First testing gave ugly waves: 7.2Vpp ugly, some strong but short ringing, not sure if the Saturn tolerates such massive spikes and I cannot be sure that the 74HC04 between the PLL and the chips can absorb them. So, since I’m an electronic n00b and I can’t properly choose components, I frantically and manually put 5 220pF capacitors in parallel – and clocks visibly straightened. 352px DOTCLK (28.6364) is the prettiest one, close to an almost perfect sine wave with a 3.7Vpp amplitude from 0, looks very good – and it’s the one I’m interested in the most. MCLK (14.318MHz) looks fine as well, not excellent but good enough.

Aside from this, all frequencies are slightly faster than they should be – 500Hz-ish faster. Not sure if this is going to cause any trouble in the long run. Hopefully not. Not really much I can do about it – that’s the level of precision the CDCE offers me. Different multipliers/divisors are not an option – I’ve tried and it just goes over the roof with both frequencies and PPM errors. So I’m just going to leave them like this for now.

Tested the S0 frequency selector pin of the 937 and it gave me a 26.847MHz 320px clock freq (close to the 26.846MHz I hoped for). Not much else to say – they all seem stable and close enough to specs.

I still have to try Goldilocks on a real NTSC model 1 Saturn with PLL instability – which I have. I’m still a bit worried about the DOTSEL level converter though (TXS0102) and input impedencies and capacitancies of target chips. Hopefully I did everything “just right” so far.

I’ll keep posting updates here.

[walter.comunello]

can I post images or videos? because it looks like I have just resurrected a Model 1 Saturn.

DOTCLK is working so far – the Saturn boots and goes into the BIOS menu. Sound is effed up because there is no CD unit attached and normally the SCSP and sound clock derive from the 33MHz crystal on the Cd drive board.

Goldilocks is still an early prototype – but it looks promising.

[walter.comunello]

so, apparently the PLL is not the only culprit in an aging Saturn. It has clock instabilities beyond the degradation of the HD49422.

I’ve seen this already – in an NTSC Mega Drive with freezing issues and in the EDCLK/VCLK degradation on a VA4 Model 1 Mega Drive with a 32X mounted. The NTSC-J Mega Drive needed a 75Ohm resistor in line with the master clock to suppress spikes, while the 32X EDCLK debacle has a dedicated, official service bulletin from SEGA (n.008, December 13, 1994). It’s about signal shapes.

Long story short, when I connected the other clocks from Goldilocks to the Saturn the system would not boot anymore. Yesterday it did boot without issues for the few times I’ve tested it. Today I’ve been doing some more in-depth testing and it would seem that since DOTCLK is the same clock that goes to the two Hitachi CPUs, Saturn issues could be divided in two aspects: video glitches and freezes.

As far as I can understand, video glitches spawn from the two VDPs, while freezes happen when the two Hitachis stumble and can’t process any more data. I had another Saturn a long time ago with seemingly a very similar problem but I dismissed it thinking it could have been a VDP RAM chip. Maybe that wasn’t necessarily the case.

DOTCLK gets out from the PLL and gets decoupled by C111, a 5pF capacitor. By probing the signal side of the capacitor the clock would stabilize a little bit and the system would boot. If not, instability would ensue. I have replaced the 5pF cap with a 15pF one.

Moreover, to combat the system freezes I’ve tried mounting a 100pF on the C95 footprint on the board (which is unpopulated, how bizarre, as if they knew something could happen). No freezes after a few minutes of menu.

I’m doing these tests with a warm system. I need to see if temperature plays a role as well.

It’s not the PLL only – it’s a more widespread issue. The PLL is just the tip of the iceberg imo.

It’s late now – more testing is needed.

[walter.comunello]

will be testing some sort of impedance matching on Goldilocks output, switching to 5V for buffers, then capacitance adjusting on each of the four MCLK zones:

 

VDP2 (IC14) and the SCU (IC5) are fed with MCLK0;

VDP1 gets MCLK1;

the two Hitachi CPUs chew on MCLK3;

the Toshiba controller has MCLK4.

 

(MCLK2 goes out through pin B66 of CN1 and has no business with the Saturn itself so I might not consider it an issue – but it’s not terminated by design and it might need some work as well.)

They all come out from the same source, have the same frequency, are driven by the same service signal (DOTSEL) and they switch at the same time, but impedance matching on this level of complexity and years after manufacturing can be tricky. A master clock going all over the place in an old device can pick up all sorts of garbage – and reflect it up the pipes. So a problem on the VDP1 end of the clock might cause the Hitachis to freeze, or vice versa. I wouldn’t be surprised if this happened.

Please let me know if any of you have any information I don’t know of. I consider myself a n00b and always in need of learning something.

• This reply was modified 2 weeks, 4 days ago by walter.comunello.

[walter.comunello]

SCSP and VDP1 are conflicting over their clocks. I believe it’s because MCLK1 has a misshapen form. I have to work out the kinks. This goes beyond the PLL, this is a more widespread problem. Clocks are degrading all over the place and to get them back in shape is nothing short of wizardry.

Edit: clocks are good, or at least as good as I can make them. Still the system struggles: after replacing a few caps (the two main elec at the bottom left and two elecs decoupling the SCSP and the VDP1) the system would almost always refuse to boot, or freeze soon after. I’m gonna try reflowing all main chips tomorrow.

I feel like I’m doing one step forward and two steps backwards. These machines are annoying.

• This reply was modified 2 weeks, 3 days ago by walter.comunello.

[walter.comunello]

Update: the system is rock solid at 28.636MHz, but it freezes randomly at 26.846MHz. Most likely I have not understood how the video clock shifts and what exactly DOTCLK does. The only thing I can do is to acquire a working Saturn and try to probe DOTCLK and all the master clocks.

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