What causes the HPLL2x phase bug?

NewHome Forums OSSC, OSSC Pro and DExx-vd isl OSSC – Discussion and support What causes the HPLL2x phase bug?

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    I decided to disable HPLL2x in all my profiles because of the weird behavior with the phase setting when it’s on, as mentioned on the wiki. Adjusting the phase, it tends to jump to random phases instead of the given setting.

    But has anyone figured out what the cause of this behavior is and if there’s a strategy for working around it with HPLL2x enabled?

    While on the subject, in HPLL2x mode, does anybody know if the TVP7002 decimates to the target sample rate through downsampling or subsampling?


    To me it just looks like a design flaw in TVP7002, i.e. PLL post-divider alignment is random instead of phase select MSB controlling it. ADC block uses the divided clock so no extra samples are taken and thus no averaging is done.

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