Omnigamer

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  • July 4, 2018 at 4:32 AM in reply to: Rate lock output modes #22309
    Omnigamer
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      It’s annoyingly difficult to find published timing characteristics for microSD flash, but best possible block erase times seem to be in the range of 2 ms, with 5 ms being more typical. Block erases can cover multiple planes in a single erase, but that’s up to the sophistication of the controller or layout scheme. Endurance can also vary pretty widely, but you’re right that 100k is typical rating, with some claiming as much as 2M. Even with a modest sized card at 10k p/e cycles, that’s quite a long period of performance before it needs replaced.

      Either way, the point stands that it would very much be dependent on the combination of card quality, encoder performance, and access timing to make it work for that scheme. It’s an interesting idea to theorize about, but from an ease perspective it may just be easier to refactor the code for either a different part or external ram blocks. It would mean manufacturing units ourselves, but that very well might be the better option over embarking on a path that has no guarantee of working.

      July 3, 2018 at 7:06 PM in reply to: Rate lock output modes #22306
      Omnigamer
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        The framebuffer is definitely not happening using only the resources on the FPGA, but what is the communication performance with the microSD slot? For sufficiently small sources and a reasonable encoding scheme, it may be possible to send source copies there and process them during output frame generation. Bandwidth limits are a lot rougher for inputs greater than 240p, but most of those sources don’t exhibit many of the same issues, so we could possibly leave them as-is.

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