OSSC v1.xx series beta firmware

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  • November 19, 2025 at 9:07 PM #67765
    Zacabeb
    Participant

      From what I know, the OSSC Classic doesn’t have any separate RAM but is limited to the memory within the FPGA itself.

      November 19, 2025 at 10:03 PM #67766
      marqs
      Participant

        marqs, I’ve been wondering about this for a while now: would it be possible to take a regular OSSC 1.8, desolder the RAM, add a similar RAM module but with higher capacity and rework the firmware to accept features such as motion adaptive deinterlacing? even if only at say, 2x

        OSSC doesn’t have any RAM chip to begin with, it only uses the limited block RAM available on FPGA. The only larger pin compatible FPGA would be EP4CE22 that has 10 additional 1kB RAM blocks, enabling only 2 extra line buffers (of 2048 pixels each). A larger quality of life improvement would be adding a clock generator on board to enable (ideally with above FPGA upgrade) A-LM functionality of Pro, even though it’d have some limitations. That would require PCB update in addition to FW fork which at this point of lifespan has high barrier.

        December 21, 2025 at 5:30 PM #68077
        marqs
        Participant

          v1.20 firmware has been now released with its dedicated thread where follow-up discussion also should take place as it’s outside of beta phase.

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