[marqs]

@JAMIEvx Tried importing the linked profile+settings pair as default but could not replicate the lockup. I regenerated bitstream with different seed which slightly changes timings within FPGA (.jic here). During development I’ve occasionally managed to generate a bitstream that similarly does not boot, but so far I’ve thought that it’d due to a tool bug and would behave identically on every board.

[marqs]

I see. After going back to 0.76, could you export profile 0 to SD card and share it with settings.bin? I can try importing those and see if I could replicate the issue (very unlikely, though).

[marqs]

@JAMIEvx interesting, it looks like that either a) both 0.70 and 0.76 are unable to update to 0.77 or b) update completes as expected but 0.77 does not boot on your board. I just added a .jic version of 0.77 on github – can you try flashing it via USB Blaster to see if that results to inability to boot as well?

[marqs]

@Cae are you able to try another SD card? For some reason the image is corrupted after it has been transferred to DRAM.

[marqs]

@JAMIEvx @BoldFusion When have you bought the board and do you remember which fw version was installed when you initiated the update? Did you start the update from test pattern or an active input? We may need to get one of these failing boards for return analysis and try to replicate the failure.

Regarding Error 9, that is listed in wiki: “Error -9: CRC error while checking the data copied to DRAM. Change to test pattern or restart the device, and try again.”.

[marqs]

If high-contrast picture content (like seen in the dialog box) disturbs sync, then cable would be my first suspect. Presumably it uses composite/luma for sync, but I’d ensure that line has 75ohm termination resistor as PAL cables should. Alternatively you can adjust analog sync Vth from OSSC Pro sync menu which may be enough to fix the issue. You may also maximize H-PLL loop gain when framelock is off to mimimize re-lock time and associated skew, but that should be used only as a last resort if you can’t solve the issue otherwise.

[marqs]

The production version is not made with Kicad, thus it takes real effort to complete placement & routing of FOSS version of the PCB. It’s bound to happen at some point, but the priority is low at the moment.

[marqs]

You can find the open version here with description of the design status in README.

[marqs]

The mod disables red led, but on V1.xx the same information is encoded in green LED. On sync options you could try adjusting analog sync Vth and/or ADC PLL BW (latter only available on v1.11).

[marqs]

Which HW revision and FW version you have? Also, does the red LED blink at the same time as the blackout?

[marqs]

The issue sounds similar to this. I can only think of max_framerate value in the transmitted metadata potentially confusing some TVs as it’s set to constant 144Hz instead of being bounded what is reported in EDID. Pro does not currently vary / extend blanking time and doing that would just add latency in itself.

[marqs]

An audio source selection similar to what is done for AV1-3 is planned.

[marqs]

It is possible, but you should also consider buying/building this passive adapter which effectively lets you repurpose Pro’s VGA input as SCART. Additionally you need fully wired VGA cable (especially pin 4) and 3.5mm cable.

[marqs]

You should be able to convert profiles between different versions (with some limitations) using this web tool: http://pbnl.byethost7.com/ossc/profiles/?i=1

[marqs]

They are not compatible with 1.11 so they won’t get loaded on it. Any time you save a profile on v1.11, it overwrites the slot in question.

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