walter.comunello

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  • May 19, 2026 at 8:13 PM in reply to: The Sega Saturn and the dreaded PLL chip #69496
    walter.comunello
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      @joostr14: if Goldilocks works (I’ve named it “Project Goldilocks”, I like how it sounds) it’ll revive dead Saturns since it aims to be a full PLL replacement in Model 1 Saturns. 937 would generate a single region frequencies whilst the 949 variant should be able imitate any region via the NPSEL point.

      937 and 949 prototypes should be ready this week. the 949 pcb has to be reworked since the 1.8V regulator footprint is wrong. But for now I’ll just see if they do anything functional.

      May 12, 2026 at 12:53 PM in reply to: The Sega Saturn and the dreaded PLL chip #69410
      walter.comunello
      Participant

        Hi,

        I’ve been following this topic for a while and I’m also interested in a replacement.

        I’m actually working on something based on CDCE PLLs. I’ve worked on schematics and I gathered all the info I thought I needed. I have the PCBs here and I’m waiting for the components to arrive. I still have to build the prototypes and see if they work.

        I have a kinda messed up NTSC Saturn that I’m fixing. As soon as I reinstall the removed chips (lots of corrupted contacts, maybe it’s been sitting in a humind environment for too long judging by the amount of rust in the CD unit metal frame) I’m gonna give it a full recap, then see if it works.

        I also have another NTSC Saturn in much better condition, with the Black Screen of Death symptom. Probing the DOTCLK frequency gives an unstable clock, which makes me think the PLL is damaged beyond acceptable tolerances. I have done nothing on it.

        What I’m planning to do is:

        1- Build the CDCE937 version of the prototype (and program the CDCE)

        1.5- I also have a CDCE949 version with NTSC+PAL support via NPSEL testpoint but I first want to see if the “base” version does anything useful, then I’ll go from there

        2- see if it works “as is” (just seeing if it outputs the frequencies I’m predicting AND if they seem stable and “pretty” enough)

        3- mount it on the system, bypassing the 14M master clock and the 33M CD output clock

        4- see if it does anything. (The module interacting with the system might need impedance adjustments that I might not know of just yet.)

         

        If it works, it won’t need the CD output freq of 33M to generate the sound clock. I hope something useful will happen.

        It’ll take a few weeks, if you’re interested I’ll keep you updated.

        I’m also interested in feedback. Do you think a CDCE- or generic PLL- based solution might work? The 315-5746 block diagram gave me all the info I needed. I just thought, “why not?”

        I basically have to hope that the output frequencies are *just right*, as Goldilocks would say, and when I say *just right* I mean the device will keep the system stable for as long as the user wants to play with it.

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